In a conventional Tri-gate LCD panel, the output voltages of each channel on source terminal of each of the transistors are the same, and the driving forces formed therefore are the same as well. To ensure the voltages of each data buses are the same when the transistors are in a solid color mode such that each pixel receives the same electrical potential, impedances of each fan-out shape trace of each channel when unit corresponding to source side of each transistor fans out the fan-out shape trace should be the same theoretically.
However, in a liquid crystal display panel with narrow border, the impedances of the traces is hardly the same because the layout area for the fan-out shape traces in the narrow border is limited. Because the layout distance on two sides of the traces is longer than that on middle of the traces, the impedance usually appears to be small in middle and big on two sides. Accordingly, voltage latency on two sides of the data bus is more serious than that on middle part of the data bus. Once the charging time of the pixel is not enough, the voltage maintained by the pixel cannot reach to an ideal voltage such that the brightness of R, G or B is dimmed. Specifically, when the liquid crystal display panel with narrow border is a single film tri-gate transistor liquid crystal display panel, serious two side color cast appears in color blending grey frame such as R+G, G+B or B+R, and the situations are greenish, bluish or reddish, respectively. It appears to be a vertical color cast block when the liquid crystal display panel is a multiple film tri-gate transistor liquid crystal display panel.
Referring to FIG. 1, which shows the diagram of data curve corresponding to the voltage variation of the channels of the source side of the transistor on middle and both side of the unit, in an example for displaying R+G color blending grey frame in the single film tri-gate transistor liquid crystal display panel, the curve corresponding to the relationship between the output voltage and the channels on three points A, B and C can be obtained. Referring to FIG. 2, the pixel voltage latency in the curves of point B and C in each side is more serious such that the rising time or the falling time of the pixel voltage is slow. When a data source outputs a R+G color blending grey frame (R: 255 grey, G: 255 grey, B: 0 grey), since color R of each pixel on each channel of point B and C cannot be charged to 255 grey and color B of the same pixel cannot be discharged to 0 grey rapidly after the voltage latency caused by the output terminal and the WOA (Wiring On Array), color cast is generated and yellow color is displayed in middle of the displayer while green color is displayed in both side of the displayer.